This application claims the benefit of a Japanese Patent Application No. 11-353729 filed Dec. 13, 1999, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to multiprocessor systems and memory access methods, and more particularly to a multiprocessor system which has a plurality of system modules connected via a crossbar module where each system module is mounted with a plurality of processors, and to a memory access method for such a multiprocessor system.
2. Description of the Related Art
In a conventional processor system, when a read request is output from one processor, a data preread access is started with respect to a main memory, simultaneously as an access to a cache memory of this one processor. When the access to the cache memory results in a mishit, the data read from the main memory to a buffer by the data preread access can be used to reduce the memory access time.
In a conventional multiprocessor system, a plurality of processor systems having the structure described above are connected via a bus. Accordingly, when reading the data from the cache memory of the processor, the data is in most cases read via the bus.
As the scale of the multiprocessor system becomes large, the data transfer path becomes extremely long. As a result, simply applying the data preread access of the conventional processor system to such a large-scale multiprocessor system may cause interference of normal data transfer. In addition, the bus may be occupied by the data preread access, to thereby deteriorate the performance of the multiprocessor system as a whole.
On the other hand, in a case where the buffer which holds the preread data is provided at a location distant from the processor which made the read request, it takes time to transfer the preread data to the processor which made the read request. In this case, it is impossible to bring out the advantageous effects of the data preread access.